1. Field of the Invention
This invention relates to a clock generating apparatus, a data transmitting/receiving apparatus and a method thereof: and is particularly concerned with a clock generating apparatus, a data transmitting/receiving apparatus and-a method thereof intended preferably for generating a non-overlap 2-phase clock signal according to a basic clock signal and transmitting and receiving data according to the 2-phase clock signal.
2. Description of the Prior Art
In a data transmitting/receiving apparatus used for a local area network system, for transmitting and receiving a serial data, employed hitherto is a method wherein a non-overlap 2-phase clock signal is generated from a basic clock signal, a master clock signal and a slave clock signal are generated from the 2-phase clock signal, serial data with the phase lagging 0.5 bits from serial data input further is generated other than the input serial data, and each serial data is transmitted according to a master clock signal or a slave clock signal.
Further, for transmitting the serial data, the serial data is transmitted in half-bits with data of a start delimiter constructed of an 8-bit long bit pattern placed ahead of the frame. Then, the serial data is received only at the time when each communication station detects the start delimiter. However, when the start delimiter is detected from a transmitted data, whether or not it indicates the start delimiter is detected from a configuration of the bit pattern. Thus, according to the method whereby the bit pattern (pattern by combination of 2 bits) is detected from the transmitted data in half-bits, there may be a case where data is read with the combination of data constructing the bit pattern shifted 0.5 bits according to how the data is input. In such case, a shift of 0.5 bits may arise on a bit boundary of the serial data. Now, therefore, a method for preventing a data error from resulting by correcting a phase of the serial data according to a master clock signal and a slave clock signal is employed when a shift occurs on the bit boundary of the serial data. That is, when a shift arises on the bit boundary when transmitting a basic serial data according to the master clock signal, serial data with the phase lagging 0.5 bits from the basic serial data is transmitted according to the slave clock signal, thereby preventing an error from arising on the data transmission.
In the aforementioned prior art, since serial data is selected for transmission according to the master clock signal and the slave clock signal, when the serial data with the phase lagging 0.5 bits from a basic serial data is selected as data for transmission, data transmission is delayed, and such delay in the data transmission becomes serious particularly in the system for which a high throughput is required of the data transmission.